1. Field of the Invention
This invention relates to a semiconductor fabrication method, and more particularly, to a method of fabricating a shallow-trench isolation (STI) structure with a rounded corner in an integrated circuit (IC) through a rapid thermal process (RTP).
2. Description of Related Art
The STI technique is a widely used semiconductor fabrication method for forming isolation structures in integrated circuits to electrically isolate the various active components formed in the integrated circuit. In the STI technique, the first step is to form a plurality of trenches at predefined locations in the substrate and then deposit an oxide into each of these trenches to form an STI structure. One major advantage of using the STI technique is that it allows high scalability to CMOS (complementary metal-oxide semiconductor) IC devices for fabrication at the submicron level of integration. In addition, it can help prevent the occurrence of the so-called bird's beak encroachment in the integrated circuit that would otherwise occur when using the conventional LOCOS (Local Oxidation of Silicon) technique to form the isolation structures.
FIGS. 1A-1D are schematic sectional diagrams used to depict the process steps involved in a conventional method for fabricating an STI structure in integrated circuits.
Referring to FIG. 1A, in the first step, a semiconductor substrate 100 is prepared. Then, after the substrate 100 is placed in a chamber filled with oxygen, a thermal oxidation process is performed on the substrate 100 so as to form a pad oxide layer 102 over the substrate 100. A mask layer 104 is then formed from silicon nitride (SiN) over the pad oxide layer 102 through a chemical-vapor deposition (CVD) process. After this, a photoresist layer (not shown) is coated over the wafer and then selectively removed in such a manner as to expose a predefined part of the wafer. Then, with the photoresist layer (not shown) serving as mask, an anisotropic etching process is performed on the wafer to etch away the unmasked portions of the mask layer 104, the pad oxide layer 102, and the substrate 100 until a predetermined depth in the substrate 100 is reached. Through this process, a trench 106 is formed in the substrate 100. After this, prior to forming liner oxide in trench 106, a pre-liner cleaning process is first performed on the exposed surfaces of the substrate 100 in trench 106 with RCA-A and a 10:1 solution of deionized water and hydrofluoric acid (HF) for a continuous period of about 60 seconds. During this process, however, a small edge part of the pad oxide layer 102 near the top rim of trench 106 in substrate 100 is undesirably etched away, resulting in the formation of a sharp corner 107 at the rim of trench 106.
Referring next to FIG. 1B, in the subsequent step, a liner oxide layer 108 is formed through a thermal oxidation process under a temperature of between 850.degree. C. to 950.degree. C. on the exposed surfaces of substrate 100 in trench 106. Since the process temperature used to form the liner oxide layer 108 is in the range of 850.degree. C. to 950.degree. C., which is relatively low, it does not cause the sharp corner 107 to be deformed into a rounded one. Since the sharp corner 107 has a very small convex curvature radius, a very high electric field can form there when an electric current is flowing through the resultant IC device. This electric filed causes undesired current leakage which in turn causes the resultant IC device to have highly deviant IV (current-to-voltage) characteristics. As a result, the resultant IC device suffers from a kink effect that considerably degrades the performance.
Referring to FIG. 1C, in the subsequent step, an insulating material, such as silicon dioxide, is deposited through a CVD process into trench 106 to a predetermined height above the pad oxide layer 102 so as to form an oxide layer 110 in trench 106 to form an STI structure 106a. Next, a densification process is performed under a temperature of about 1,000.degree. C. to densify the oxide layer 110 in the STI structure 106a. After this, the entire mask layer 104 is removed.
Referring next to FIG. 1D, in the subsequent step, a wet-etching process is performed on the wafer to remove the entire pad oxide layer 102 over the substrate 100. Since this wet-etching process is isotropic, it also causes a lateral part of the oxide layer 110 above the topmost surface of the substrate 100 to be etched away. This causes the topmost surface of the liner oxide layer 108 to be etched away. As a result, a groove 112 is formed in the top surface of the liner oxide layer 108, causing the sharp corner 107 to be exposed.
FIG. 2 shows an enlarged view of the groove 112 and the sharp corner 107 in the fabricated wafer of FIG. 1D. As shown, since the sharp corner 107 has a very small convex radius of curvature, a high electrical field can occur at the sharp corner 107 when the resultant IC device is in operation, thus causing a leakage current to be produced at the sharp corner 107. This leakage current then causes the resultant IC device to have highly deviant IV characteristics. More specifically, under the same voltage supply, the induced current is be reduced in magnitude due to the existence of the above-mentioned leakage current. As a result, the resultant IC device suffers from a kink effect in subthreshold voltage that considerably degrades the performance of the resultant IC device.
There exists, therefore, a need in the semiconductor industry for a method to fabricate an STI structure with a rounded corner. One such solution is disclosed in the technical paper, A Highly Manufacturable Comer Rounding Solution for 0.18 .mu.m Shallow Trench Isolation" proposed by C. P. Chang and C. S. Pai, et al. By this corner rounding solution, such techniques as Trench Etch, High Temperature Liner (above 1,100.degree. C.), and Post CMP Re-Oxidation are used to form an STI structure with a rounded corner in integrated circuit. These techniques, however, are either too difficult to carry out or too costly in thermal budget to implement.